ArchitectureSpecificsMemo - Revision history

Taavi: Imported from Moin

2025-07-20T14:13:31Z

Imported from Moin

← Older revision		Revision as of 14:13, 20 July 2025
Line 1:		Line 1:
			{{Imported from Moin}}

	__TOC__		__TOC__

Zeha at 22:04, 18 July 2025

2025-07-18T22:04:37Z

← Older revision		Revision as of 22:04, 18 July 2025
Line 3:		Line 3:
	This page is a '''draft'''. Please help enhancing it by adding lines and filling tables. Comments at the bottom of the text are also welcome.		This page is a '''draft'''. Please help enhancing it by adding lines and filling tables. Comments at the bottom of the text are also welcome.

	This is just a quick ~~array~~ to recall some of the specifics of the architectures found in the Debian project.		This is just a quick list to recall some of the specifics of the architectures found in the Debian project.

	{\| class="wikitable"		{\| class="wikitable"
Line 150:		Line 150:
	\|\|8		\|\|8
	\|\|16(8)		\|\|16(8)
	The RV64 ISA spec defines long double as 16 bytes, but older toolchains (pre-"riscv-gcc-6.1.0") have implemented long double as 8 bytes on RV64; cf. https://github.com/riscv/riscv-gcc/commit/54b21fc5ae83cefec44bc2caed4a8c664c274ba0		<small>The RV64 ISA spec defines long double as 16 bytes, but older toolchains (pre-"riscv-gcc-6.1.0") have implemented long double as 8 bytes on RV64; cf. https://github.com/riscv/riscv-gcc/commit/54b21fc5ae83cefec44bc2caed4a8c664c274ba0</small>
	\|\|16\|\|unsigned\|\|LE\|\|down		\|\|16\|\|unsigned\|\|LE\|\|down
	\|\|4K		\|\|4K

Zeha at 22:03, 18 July 2025

2025-07-18T22:03:54Z

← Older revision		Revision as of 22:03, 18 July 2025
Line 27:		Line 27:
	!stack grows		!stack grows
	!page sizes		!page sizes
	User-visible page size returned by <code>getauxval(AT_PAGESZ)</code> or <code>getconf PAGESIZE</code>, the granularity of the memory map		<small>User-visible page size returned by <code>getauxval(AT_PAGESZ)</code> or <code>getconf PAGESIZE</code>, the granularity of the memory map</small>
	!float		!float
	H=hard, S=soft, P=partial, +=excess precision, ~=not usual standard		H=hard, S=soft, P=partial, +=excess precision, ~=not usual standard
	!double		!double
	Note that the columns refer to C types. H=hard, S=soft, P=partial, +=excess precision, ~=not usual standard)		<small>Note that the columns refer to C types. H=hard, S=soft, P=partial, +=excess precision, ~=not usual standard)</small>
	!long double		!long double
	Note that the columns refer to C types. H=hard, S=soft, P=partial, +=excess precision,-=long double precision < __float128, ~=not usual standard)		<small>Note that the columns refer to C types. H=hard, S=soft, P=partial, +=excess precision,-=long double precision < __float128, ~=not usual standard)</small>
	!sizeof(time_t)		!sizeof(time_t)
	With <code>_TIME_BITS=64</code> the size is 8 on all archs		<small>With <code>_TIME_BITS=64</code> the size is 8 on all archs</small>
	!GCC pre-defined macro(s)		!GCC pre-defined macro(s)

Line 151:		Line 151:
	\|\|16(8)		\|\|16(8)
	The RV64 ISA spec defines long double as 16 bytes, but older toolchains (pre-"riscv-gcc-6.1.0") have implemented long double as 8 bytes on RV64; cf. https://github.com/riscv/riscv-gcc/commit/54b21fc5ae83cefec44bc2caed4a8c664c274ba0		The RV64 ISA spec defines long double as 16 bytes, but older toolchains (pre-"riscv-gcc-6.1.0") have implemented long double as 8 bytes on RV64; cf. https://github.com/riscv/riscv-gcc/commit/54b21fc5ae83cefec44bc2caed4a8c664c274ba0
	\|\|16\|\|unsigned\|\|LE\|\|down\|\|4K 4k is the default page size on all RISC-V systems. Depending on the chosen virtual memory mode (Sv32/Sv39/Sv48) additional page sizes are available as well: Sv32 supports 4k and 4M pages, Sv39 supports 4k, 2M and 1G pages and Sv48 supports 4k, 2M, 1G, and 512G pages \|\|H \|\|H \|\|H~\|\|8		\|\|16\|\|unsigned\|\|LE\|\|down
			\|\|4K
			<small>4k is the default page size on all RISC-V systems. Depending on the chosen virtual memory mode (Sv32/Sv39/Sv48) additional page sizes are available as well: Sv32 supports 4k and 4M pages, Sv39 supports 4k, 2M and 1G pages and Sv48 supports 4k, 2M, 1G, and 512G pages</small>
			\|\|H \|\|H \|\|H~\|\|8
	\|\|<code>__riscv && __riscv_xlen==64</code>		\|\|<code>__riscv && __riscv_xlen==64</code>
	Older, pre-mainline RISC-V toolchains used <code>__riscv__ && __riscv64</code>		Older, pre-mainline RISC-V toolchains used <code>__riscv__ && __riscv64</code>
Line 197:		Line 200:
	!ld.so(8)		!ld.so(8)
	!uname -m		!uname -m
	Used to classify CPU architectures in CMake and many ad-hoc build systems, but note that this is a kernel and/or libc specific name despite referring to the CPU		<small>Used to classify CPU architectures in CMake and many ad-hoc build systems, but note that this is a kernel and/or libc specific name despite referring to the CPU</small>
	!Meson		!Meson
	[https://mesonbuild.com/Reference-tables.html Reference table] of Meson hardware architecture names		<small>[https://mesonbuild.com/Reference-tables.html Reference table] of Meson hardware architecture names</small>
	!qemu		!qemu
	e.g. i386 results in qemu(-system)-i386(-static)		<small>e.g. i386 results in qemu(-system)-i386(-static)</small>

	\|-		\|-
Line 409:		Line 412:
	Example:		Example:

	* `unsigned char c;` - explicit unsigned, 0 <= c <= 255		* <code>unsigned char c;</code> - explicit unsigned, 0 <= c <= 255
	* `signed char c;` - explicit signed, -128 <= c <= 127		* <code>signed char c;</code> - explicit signed, -128 <= c <= 127
	* `char c;` - implicit (un)signedness, depending on architecture		* <code>char c;</code> - implicit (un)signedness, depending on architecture

	To force a signedness, either declare it explicitly or use the gcc command line option -f(un)signed-char. The gcc defaults differ only due to optimisation. Other compilers may not have this issue.		To force a signedness, either declare it explicitly or use the gcc command line option <tt>-f(un)signed-char</tt>. The gcc defaults differ only due to optimisation. Other compilers may not have this issue.

	= Architecture baselines =		= Architecture baselines =

	Each Debian architecture has a ''baseline'' indicating the oldest or least capable CPU on which the architecture can be used. The baseline can change between Debian releases. The baseline is mostly defined by the gcc-''N'' package, which is configured to produce baseline binaries when options like -march= are not used.		Each Debian architecture has a ''baseline'' indicating the oldest or least capable CPU on which the architecture can be used. The baseline can change between Debian releases. The baseline is mostly defined by the gcc-''N'' package, which is configured to produce baseline binaries when options like <tt>-march=</tt> are not used.

	If a package uses options that enable additional CPU features such as -msse in particular source files, then the maintainer of that package is responsible for [[InstructionSelection\|making sure those CPU features are only used on CPUs that support them]]. ioquake3's Altivec support on PowerPC is an example of this technique.		If a package uses options that enable additional CPU features such as -msse in particular source files, then the maintainer of that package is responsible for [[InstructionSelection\|making sure those CPU features are only used on CPUs that support them]]. ioquake3's Altivec support on PowerPC is an example of this technique.
Line 423:		Line 426:
	== amd64 ==		== amd64 ==

	x86_64 with no optional extensions (psABI baseline). The core specification includes MMX, SSE and SSE2 so these are OK, but SSE3 and up are not guaranteed. (The default is ''-march=x86-64'', but not ''-march=x86-64-v2'' or later.)		x86_64 with no optional extensions (psABI baseline). The core specification includes MMX, SSE and SSE2 so these are OK, but SSE3 and up are not guaranteed. (The default is <tt>-march=x86-64</tt>, but not <tt>-march=x86-64-v2</tt> or later.)

	See [https://gitlab.com/x86-psABIs/x86-64-ABI/-/jobs/artifacts/master/raw/x86-64-ABI/abi.pdf?job=build psABI (Table 3.1: Micro-Architecture Levels)] for amd64 ABI level. Wikipedia summary: https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels		See [https://gitlab.com/x86-psABIs/x86-64-ABI/-/jobs/artifacts/master/raw/x86-64-ABI/abi.pdf?job=build psABI (Table 3.1: Micro-Architecture Levels)] for amd64 ABI level. Wikipedia summary: https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels
Line 429:		Line 432:
	== arc ==		== arc ==

	A fully featured ARC HS with additional support for double-precision FPU ("-mcpu=hs38_linux"). And this is a default "-mcpu" for ARC starting from GCC 11.		A fully featured ARC HS with additional support for double-precision FPU (<tt>-mcpu=hs38_linux</tt>). And this is a default <tt>-mcpu</tt> for ARC starting from GCC 11.

	To be more precise it's a baseline ARC HS with HW division ("-mdiv-rem"), atomic instructions ("-matomic"), 64-bit loads/stores ("-mll64"), the most advanced multiplier (including quad half-word & vector operations, "-mmpy-option=plus_qmacw") and double-precision FPU ("-mfpu=fpud_all").		To be more precise it's a baseline ARC HS with HW division (<tt>-mdiv-rem</tt>), atomic instructions (<tt>-matomic</tt>), 64-bit loads/stores (<tt>-mll64</tt>), the most advanced multiplier (including quad half-word & vector operations, <tt>-mmpy-option=plus_qmacw</tt>) and double-precision FPU (<tt>-mfpu=fpud_all</tt>).

	== arm64 ==		== arm64 ==

Zeha at 21:58, 18 July 2025

2025-07-18T21:58:45Z

← Older revision		Revision as of 21:58, 18 July 2025
Line 575:		Line 575:
	= See also =		= See also =

	* Information about [Haskell/GHC Haskell] on different architectures.		* Information about [[Haskell/GHC Haskell]] on different architectures.
	* [https://github.com/cpredef/predef/blob/master/Architectures.md Pre-defined Compiler Macros Wiki - Architectures]		* [https://github.com/cpredef/predef/blob/master/Architectures.md Pre-defined Compiler Macros Wiki - Architectures]
	* [https://gcc.gnu.org/onlinedocs/cpp/Predefined-Macros.html GCC Predefined Macros]		* [https://gcc.gnu.org/onlinedocs/cpp/Predefined-Macros.html GCC Predefined Macros]
	* [InstructionSelection Instruction Selection]		* [[InstructionSelection\|Instruction Selection]]
	* [Multiarch/Tuples]]		* [[Multiarch/Tuples]]

	[[Category:Ports]]		[[Category:Ports]]

Zeha at 21:56, 18 July 2025

2025-07-18T21:56:27Z

← Older revision		Revision as of 21:56, 18 July 2025
Line 196:		Line 196:
	!ELF machine EM_		!ELF machine EM_
	!ld.so(8)		!ld.so(8)
	!uname -~~mUsed~~ to classify CPU architectures in CMake and many ad-hoc build systems, but note that this is a kernel and/or libc specific name despite referring to the CPU		!uname -m
	!Meson[https://mesonbuild.com/Reference-tables.html Reference table] of Meson hardware architecture names		Used to classify CPU architectures in CMake and many ad-hoc build systems, but note that this is a kernel and/or libc specific name despite referring to the CPU
	!~~qemue~~.g. i386 results in qemu(-system)-i386(-static)		!Meson
			[https://mesonbuild.com/Reference-tables.html Reference table] of Meson hardware architecture names
			!qemu
			e.g. i386 results in qemu(-system)-i386(-static)

	\|-		\|-

Zeha at 21:54, 18 July 2025

2025-07-18T21:54:27Z

← Older revision		Revision as of 21:54, 18 July 2025
Line 152:		Line 152:
	The RV64 ISA spec defines long double as 16 bytes, but older toolchains (pre-"riscv-gcc-6.1.0") have implemented long double as 8 bytes on RV64; cf. https://github.com/riscv/riscv-gcc/commit/54b21fc5ae83cefec44bc2caed4a8c664c274ba0		The RV64 ISA spec defines long double as 16 bytes, but older toolchains (pre-"riscv-gcc-6.1.0") have implemented long double as 8 bytes on RV64; cf. https://github.com/riscv/riscv-gcc/commit/54b21fc5ae83cefec44bc2caed4a8c664c274ba0
	\|\|16\|\|unsigned\|\|LE\|\|down\|\|4K 4k is the default page size on all RISC-V systems. Depending on the chosen virtual memory mode (Sv32/Sv39/Sv48) additional page sizes are available as well: Sv32 supports 4k and 4M pages, Sv39 supports 4k, 2M and 1G pages and Sv48 supports 4k, 2M, 1G, and 512G pages \|\|H \|\|H \|\|H~\|\|8		\|\|16\|\|unsigned\|\|LE\|\|down\|\|4K 4k is the default page size on all RISC-V systems. Depending on the chosen virtual memory mode (Sv32/Sv39/Sv48) additional page sizes are available as well: Sv32 supports 4k and 4M pages, Sv39 supports 4k, 2M and 1G pages and Sv48 supports 4k, 2M, 1G, and 512G pages \|\|H \|\|H \|\|H~\|\|8
	\|\|<code>__riscv && __riscv_xlen==64</code> Older, pre-mainline RISC-V toolchains used <code>__riscv__ && __riscv64</code>		\|\|<code>__riscv && __riscv_xlen==64</code>
			Older, pre-mainline RISC-V toolchains used <code>__riscv__ && __riscv64</code>

	\|-		\|-

Zeha at 21:53, 18 July 2025

2025-07-18T21:53:47Z

← Older revision		Revision as of 21:53, 18 July 2025
Line 215:		Line 215:

	\|-		\|-
	\|\|'''arm''' \|\|arm-linux-gnu \|\|32\|\|ARM\|\|/lib/ld-linux.so.2\|\|arm*Many names starting with arm, e.g. armv5tel\|\|arm\|\|arm		\|\|'''arm''' \|\|arm-linux-gnu \|\|32\|\|ARM\|\|/lib/ld-linux.so.2
			\|\|arm*
			Many names starting with arm, e.g. armv5tel
			\|\|arm
			\|\|arm

	\|-		\|-

Zeha at 21:52, 18 July 2025

2025-07-18T21:52:52Z

← Older revision		Revision as of 21:52, 18 July 2025
Line 49:		Line 49:
	\|\|'''any-amd64, amd64, kfreebsd-amd64, hurd-amd64''' \|\|8\|\|16\|\|16\|\|signed\|\|LE\|\|down\|\|4K \|\|H\|\|H		\|\|'''any-amd64, amd64, kfreebsd-amd64, hurd-amd64''' \|\|8\|\|16\|\|16\|\|signed\|\|LE\|\|down\|\|4K \|\|H\|\|H
	\|\|H-		\|\|H-
	Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]		Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]
	\|\|8		\|\|8
	\|\|<code>__x86_64__ && __LP64__</code> it's a common gotcha for x32, you need to use <code>__LP64__</code>/<code>__ILP32__</code> to tell them apart		\|\|<code>__x86_64__ && __LP64__</code> it's a common gotcha for x32, you need to use <code>__LP64__</code>/<code>__ILP32__</code> to tell them apart
Line 351:		Line 351:
	== avr32 ==		== avr32 ==

	Unaligned access is ok for 32bits word but not for 16bits or 64bits word see[https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/avr32/include/asm/unaligned.h kernel source]		Unaligned access is ok for 32bits word but not for 16bits or 64bits word see [https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/avr32/include/asm/unaligned.h kernel source]

	== i386/x32/amd64 ==		== i386/x32/amd64 ==

Zeha at 21:51, 18 July 2025

2025-07-18T21:51:52Z

← Older revision		Revision as of 21:51, 18 July 2025
Line 27:		Line 27:
	!stack grows		!stack grows
	!page sizes		!page sizes
	User-visible page size returned by `getauxval(AT_PAGESZ)` or `getconf PAGESIZE`, the granularity of the memory map		User-visible page size returned by <code>getauxval(AT_PAGESZ)</code> or <code>getconf PAGESIZE</code>, the granularity of the memory map
	!float		!float
	H=hard, S=soft, P=partial, +=excess precision, ~=not usual standard		H=hard, S=soft, P=partial, +=excess precision, ~=not usual standard
Line 35:		Line 35:
	Note that the columns refer to C types. H=hard, S=soft, P=partial, +=excess precision,-=long double precision < __float128, ~=not usual standard)		Note that the columns refer to C types. H=hard, S=soft, P=partial, +=excess precision,-=long double precision < __float128, ~=not usual standard)
	!sizeof(time_t)		!sizeof(time_t)
	With <code>_TIME_BITS=64</code> the size is 8 on all archs)		With <code>_TIME_BITS=64</code> the size is 8 on all archs
	!GCC pre-defined macro(s)		!GCC pre-defined macro(s)

	\|-		\|-
	\|\|'''alpha''' \|\|8\|\|16 long double changed size from 8 to 16 in Lenny)\|\|16\|\|signed\|\|LE\|\|down\|\|8K\|\|?\|\|?\|\|?\|\|8		\|\|'''alpha'''
			\|\|8
			\|\|16
			long double changed size from 8 to 16 in Lenny
			\|\|16\|\|signed\|\|LE\|\|down\|\|8K\|\|?\|\|?\|\|?\|\|8
	\|\|<code>__alpha__</code>		\|\|<code>__alpha__</code>

Line 47:		Line 51:
	Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]		Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]
	\|\|8		\|\|8
	\|\|<code>__x86_64__ && __LP64__</code> it's a common gotcha for x32, you need to use <code>__LP64__</code>/<code>__ILP32__</code> to tell them apart)		\|\|<code>__x86_64__ && __LP64__</code> it's a common gotcha for x32, you need to use <code>__LP64__</code>/<code>__ILP32__</code> to tell them apart

	\|-		\|-
Line 82:		Line 86:

	\|-		\|-
	\|\|'''any-i386i386, kfreebsd-i386, hurd-i386)''' \|\| 4\|\|12\|\|168 prior to GCC 7)\|\| signed\|\|LE\|\|down\|\|4K \|\|H+\|\|H+		\|\|'''any-i386i386, kfreebsd-i386, hurd-i386''' \|\| 4\|\|12\|\|168 prior to GCC 7\|\| signed\|\|LE\|\|down\|\|4K \|\|H+\|\|H+
	\|\|H-		\|\|H-
	Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]		Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]
Line 91:		Line 95:
	\|\|'''ia64''' \|\|8 \|\|16\|\|16\|\| signed\|\|LE		\|\|'''ia64''' \|\|8 \|\|16\|\|16\|\| signed\|\|LE
	\|\|both		\|\|both
	The conventional stack grows down from the top of the stack mapping, but there is also the Register Backing Store which grows up from the bottom of the stack mapping at the same time)		The conventional stack grows down from the top of the stack mapping, but there is also the Register Backing Store which grows up from the bottom of the stack mapping at the same time
	\|\|? \|\|H \|\|H \|\|H \|\|8		\|\|? \|\|H \|\|H \|\|H \|\|8
	\|\|<code>__ia64__</code>		\|\|<code>__ia64__</code>

Zeha at 21:50, 18 July 2025

2025-07-18T21:50:11Z

← Older revision		Revision as of 21:50, 18 July 2025
Line 39:		Line 39:

	\|-		\|-
	\|\|'''alpha''' \|\|8\|\|~~16long~~ double changed size from 8 to 16 in Lenny)\|\|16\|\|signed\|\|LE\|\|down\|\|8K\|\|?\|\|?\|\|?\|\|8		\|\|'''alpha''' \|\|8\|\|16 long double changed size from 8 to 16 in Lenny)\|\|16\|\|signed\|\|LE\|\|down\|\|8K\|\|?\|\|?\|\|?\|\|8
	\|\|<code>__alpha__</code>		\|\|<code>__alpha__</code>

	\|-		\|-
	\|\|'''any-amd64, amd64, kfreebsd-amd64, hurd-amd64''' \|\|8\|\|16\|\|16\|\|signed\|\|LE\|\|down\|\|4K \|\|H\|\|H\|\|H- Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]\|\|8		\|\|'''any-amd64, amd64, kfreebsd-amd64, hurd-amd64''' \|\|8\|\|16\|\|16\|\|signed\|\|LE\|\|down\|\|4K \|\|H\|\|H
			\|\|H-
			Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]
			\|\|8
	\|\|<code>__x86_64__ && __LP64__</code> it's a common gotcha for x32, you need to use <code>__LP64__</code>/<code>__ILP32__</code> to tell them apart)		\|\|<code>__x86_64__ && __LP64__</code> it's a common gotcha for x32, you need to use <code>__LP64__</code>/<code>__ILP32__</code> to tell them apart)

Line 79:		Line 82:

	\|-		\|-
	\|\|'''any-i386i386, kfreebsd-i386, hurd-i386)''' \|\| 4\|\|12\|\|168 prior to GCC 7)\|\| signed\|\|LE\|\|down\|\|4K \|\|H+\|\|H+\|\|H- Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision])\|\|4		\|\|'''any-i386i386, kfreebsd-i386, hurd-i386)''' \|\| 4\|\|12\|\|168 prior to GCC 7)\|\| signed\|\|LE\|\|down\|\|4K \|\|H+\|\|H+
			\|\|H-
			Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]
			\|\|4
	\|\|<code>__i386__</code>		\|\|<code>__i386__</code>

	\|-		\|-
	\|\|'''ia64''' \|\|8 \|\|16\|\|16\|\| signed\|\|LE\|\|~~bothThe~~ conventional stack grows down from the top of the stack mapping, but there is also the Register Backing Store which grows up from the bottom of the stack mapping at the same time)\|\|? \|\|H \|\|H \|\|H \|\|8		\|\|'''ia64''' \|\|8 \|\|16\|\|16\|\| signed\|\|LE
			\|\|both
			The conventional stack grows down from the top of the stack mapping, but there is also the Register Backing Store which grows up from the bottom of the stack mapping at the same time)
			\|\|? \|\|H \|\|H \|\|H \|\|8
	\|\|<code>__ia64__</code>		\|\|<code>__ia64__</code>

Line 95:		Line 104:

	\|-		\|-
	\|\|'''mips ~~There are also 6 mipsr6 ports: see [MipsRev6]~~''' \|\|4 \|\|8 \|\|8\|\| signed\|\|BE\|\|down\|\|4K-64K \|\|H \|\|H \|\|H \|\|4		\|\|'''mips''' \|\|4 \|\|8 \|\|8\|\| signed\|\|BE\|\|down\|\|4K-64K \|\|H \|\|H \|\|H \|\|4
	\|\|<code>__mips__ && _MIPSEB && _MIPS_SIM==_ABIO32</code>		\|\|<code>__mips__ && _MIPSEB && _MIPS_SIM==_ABIO32</code>

Line 119:		Line 128:

	\|-		\|-
	\|\|'''powerpc''' \|\|4 \|\|~~16long~~ double changed size from 8 to 16 in Lenny) \|\|16\|\| unsigned\|\|BE\|\|down\|\|4K-64K \|\|? \|\|? \|\|? \|\|4		\|\|'''powerpc''' \|\|4
			\|\|16
			long double changed size from 8 to 16 in Lenny
			\|\|16\|\| unsigned\|\|BE\|\|down\|\|4K-64K \|\|? \|\|? \|\|? \|\|4
	\|\|<code>__powerpc__</code>		\|\|<code>__powerpc__</code>

Line 131:		Line 143:

	\|-		\|-
	\|\|'''riscv64''' \|\|8 \|\|16(8)The RV64 ISA spec defines long double as 16 bytes, but older toolchains (pre-"riscv-gcc-6.1.0") have implemented long double as 8 bytes on RV64; cf. https://github.com/riscv/riscv-gcc/commit/54b21fc5ae83cefec44bc2caed4a8c664c274ba0\|\|16\|\|unsigned\|\|LE\|\|down\|\|4K 4k is the default page size on all RISC-V systems. Depending on the chosen virtual memory mode (Sv32/Sv39/Sv48) additional page sizes are available as well: Sv32 supports 4k and 4M pages, Sv39 supports 4k, 2M and 1G pages and Sv48 supports 4k, 2M, 1G, and 512G pages \|\|H \|\|H \|\|H~\|\|8		\|\|'''riscv64'''
			\|\|8
			\|\|16(8)
			The RV64 ISA spec defines long double as 16 bytes, but older toolchains (pre-"riscv-gcc-6.1.0") have implemented long double as 8 bytes on RV64; cf. https://github.com/riscv/riscv-gcc/commit/54b21fc5ae83cefec44bc2caed4a8c664c274ba0
			\|\|16\|\|unsigned\|\|LE\|\|down\|\|4K 4k is the default page size on all RISC-V systems. Depending on the chosen virtual memory mode (Sv32/Sv39/Sv48) additional page sizes are available as well: Sv32 supports 4k and 4M pages, Sv39 supports 4k, 2M and 1G pages and Sv48 supports 4k, 2M, 1G, and 512G pages \|\|H \|\|H \|\|H~\|\|8
	\|\|<code>__riscv && __riscv_xlen==64</code> Older, pre-mainline RISC-V toolchains used <code>__riscv__ && __riscv64</code>		\|\|<code>__riscv && __riscv_xlen==64</code> Older, pre-mainline RISC-V toolchains used <code>__riscv__ && __riscv64</code>

	\|-		\|-
	\|\|'''s390''' \|\|4\|\|~~16long~~ double changed size from 8 to 16 in Lenny \|\|?\|\| unsigned\|\|BE\|\|down\|\|? \|\|? \|\|? \|\|? \|\|4		\|\|'''s390''' \|\|4
			\|\|16
			long double changed size from 8 to 16 in Lenny
			\|\|?\|\| unsigned\|\|BE\|\|down\|\|? \|\|? \|\|? \|\|? \|\|4
	\|\|<code>__s390__</code>		\|\|<code>__s390__</code>

Line 147:		Line 166:

	\|-		\|-
	\|\|'''sparc''' \|\|4 \|\|~~16long~~ double changed size from 8 to 16 in Lenny \|\|?\|\| signed\|\|BE\|\|down\|\|? \|\|? \|\|? \|\|? \|\|4		\|\|'''sparc''' \|\|4
			\|\|16
			long double changed size from 8 to 16 in Lenny
			\|\|?\|\| signed\|\|BE\|\|down\|\|? \|\|? \|\|? \|\|? \|\|4
	\|\|<code>__sparc__</code>		\|\|<code>__sparc__</code>

Line 155:		Line 177:

	\|-		\|-
	\|\|'''x32''' \|\|4 \|\|16\|\|16\|\| signed\|\|LE\|\|down\|\|4K \|\|H \|\|H \|\|H- Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]\|\|8		\|\|'''x32''' \|\|4 \|\|16\|\|16\|\| signed\|\|LE\|\|down\|\|4K \|\|H \|\|H
			\|\|H-
			Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]
			\|\|8
	\|\|<code>__x86_64__ && __ILP32__</code>		\|\|<code>__x86_64__ && __ILP32__</code>
	\|}		\|}

← Older revision		Revision as of 21:50, 18 July 2025
Line 39:		Line 39:

	\|-		\|-
	\|\|'''alpha''' \|\|8\|\|~~16long~~ double changed size from 8 to 16 in Lenny)\|\|16\|\|signed\|\|LE\|\|down\|\|8K\|\|?\|\|?\|\|?\|\|8		\|\|'''alpha''' \|\|8\|\|16 long double changed size from 8 to 16 in Lenny)\|\|16\|\|signed\|\|LE\|\|down\|\|8K\|\|?\|\|?\|\|?\|\|8
	\|\|<code>__alpha__</code>		\|\|<code>__alpha__</code>

	\|-		\|-
	\|\|'''any-amd64, amd64, kfreebsd-amd64, hurd-amd64''' \|\|8\|\|16\|\|16\|\|signed\|\|LE\|\|down\|\|4K \|\|H\|\|H\|\|H- Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]\|\|8		\|\|'''any-amd64, amd64, kfreebsd-amd64, hurd-amd64''' \|\|8\|\|16\|\|16\|\|signed\|\|LE\|\|down\|\|4K \|\|H\|\|H
			\|\|H-
			Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]
			\|\|8
	\|\|<code>__x86_64__ && __LP64__</code> it's a common gotcha for x32, you need to use <code>__LP64__</code>/<code>__ILP32__</code> to tell them apart)		\|\|<code>__x86_64__ && __LP64__</code> it's a common gotcha for x32, you need to use <code>__LP64__</code>/<code>__ILP32__</code> to tell them apart)

Line 79:		Line 82:

	\|-		\|-
	\|\|'''any-i386i386, kfreebsd-i386, hurd-i386)''' \|\| 4\|\|12\|\|168 prior to GCC 7)\|\| signed\|\|LE\|\|down\|\|4K \|\|H+\|\|H+\|\|H- Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision])\|\|4		\|\|'''any-i386i386, kfreebsd-i386, hurd-i386)''' \|\| 4\|\|12\|\|168 prior to GCC 7)\|\| signed\|\|LE\|\|down\|\|4K \|\|H+\|\|H+
			\|\|H-
			Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]
			\|\|4
	\|\|<code>__i386__</code>		\|\|<code>__i386__</code>

	\|-		\|-
	\|\|'''ia64''' \|\|8 \|\|16\|\|16\|\| signed\|\|LE\|\|~~bothThe~~ conventional stack grows down from the top of the stack mapping, but there is also the Register Backing Store which grows up from the bottom of the stack mapping at the same time)\|\|? \|\|H \|\|H \|\|H \|\|8		\|\|'''ia64''' \|\|8 \|\|16\|\|16\|\| signed\|\|LE
			\|\|both
			The conventional stack grows down from the top of the stack mapping, but there is also the Register Backing Store which grows up from the bottom of the stack mapping at the same time)
			\|\|? \|\|H \|\|H \|\|H \|\|8
	\|\|<code>__ia64__</code>		\|\|<code>__ia64__</code>

Line 95:		Line 104:

	\|-		\|-
	\|\|'''mips ~~There are also 6 mipsr6 ports: see [MipsRev6]~~''' \|\|4 \|\|8 \|\|8\|\| signed\|\|BE\|\|down\|\|4K-64K \|\|H \|\|H \|\|H \|\|4		\|\|'''mips''' \|\|4 \|\|8 \|\|8\|\| signed\|\|BE\|\|down\|\|4K-64K \|\|H \|\|H \|\|H \|\|4
	\|\|<code>__mips__ && _MIPSEB && _MIPS_SIM==_ABIO32</code>		\|\|<code>__mips__ && _MIPSEB && _MIPS_SIM==_ABIO32</code>

Line 119:		Line 128:

	\|-		\|-
	\|\|'''powerpc''' \|\|4 \|\|~~16long~~ double changed size from 8 to 16 in Lenny) \|\|16\|\| unsigned\|\|BE\|\|down\|\|4K-64K \|\|? \|\|? \|\|? \|\|4		\|\|'''powerpc''' \|\|4
			\|\|16
			long double changed size from 8 to 16 in Lenny
			\|\|16\|\| unsigned\|\|BE\|\|down\|\|4K-64K \|\|? \|\|? \|\|? \|\|4
	\|\|<code>__powerpc__</code>		\|\|<code>__powerpc__</code>

Line 131:		Line 143:

	\|-		\|-
	\|\|'''riscv64''' \|\|8 \|\|16(8)The RV64 ISA spec defines long double as 16 bytes, but older toolchains (pre-"riscv-gcc-6.1.0") have implemented long double as 8 bytes on RV64; cf. https://github.com/riscv/riscv-gcc/commit/54b21fc5ae83cefec44bc2caed4a8c664c274ba0\|\|16\|\|unsigned\|\|LE\|\|down\|\|4K 4k is the default page size on all RISC-V systems. Depending on the chosen virtual memory mode (Sv32/Sv39/Sv48) additional page sizes are available as well: Sv32 supports 4k and 4M pages, Sv39 supports 4k, 2M and 1G pages and Sv48 supports 4k, 2M, 1G, and 512G pages \|\|H \|\|H \|\|H~\|\|8		\|\|'''riscv64'''
			\|\|8
			\|\|16(8)
			The RV64 ISA spec defines long double as 16 bytes, but older toolchains (pre-"riscv-gcc-6.1.0") have implemented long double as 8 bytes on RV64; cf. https://github.com/riscv/riscv-gcc/commit/54b21fc5ae83cefec44bc2caed4a8c664c274ba0
			\|\|16\|\|unsigned\|\|LE\|\|down\|\|4K 4k is the default page size on all RISC-V systems. Depending on the chosen virtual memory mode (Sv32/Sv39/Sv48) additional page sizes are available as well: Sv32 supports 4k and 4M pages, Sv39 supports 4k, 2M and 1G pages and Sv48 supports 4k, 2M, 1G, and 512G pages \|\|H \|\|H \|\|H~\|\|8
	\|\|<code>__riscv && __riscv_xlen==64</code> Older, pre-mainline RISC-V toolchains used <code>__riscv__ && __riscv64</code>		\|\|<code>__riscv && __riscv_xlen==64</code> Older, pre-mainline RISC-V toolchains used <code>__riscv__ && __riscv64</code>

	\|-		\|-
	\|\|'''s390''' \|\|4\|\|~~16long~~ double changed size from 8 to 16 in Lenny \|\|?\|\| unsigned\|\|BE\|\|down\|\|? \|\|? \|\|? \|\|? \|\|4		\|\|'''s390''' \|\|4
			\|\|16
			long double changed size from 8 to 16 in Lenny
			\|\|?\|\| unsigned\|\|BE\|\|down\|\|? \|\|? \|\|? \|\|? \|\|4
	\|\|<code>__s390__</code>		\|\|<code>__s390__</code>

Line 147:		Line 166:

	\|-		\|-
	\|\|'''sparc''' \|\|4 \|\|~~16long~~ double changed size from 8 to 16 in Lenny \|\|?\|\| signed\|\|BE\|\|down\|\|? \|\|? \|\|? \|\|? \|\|4		\|\|'''sparc''' \|\|4
			\|\|16
			long double changed size from 8 to 16 in Lenny
			\|\|?\|\| signed\|\|BE\|\|down\|\|? \|\|? \|\|? \|\|? \|\|4
	\|\|<code>__sparc__</code>		\|\|<code>__sparc__</code>

Line 155:		Line 177:

	\|-		\|-
	\|\|'''x32''' \|\|4 \|\|16\|\|16\|\| signed\|\|LE\|\|down\|\|4K \|\|H \|\|H \|\|H- Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]\|\|8		\|\|'''x32''' \|\|4 \|\|16\|\|16\|\| signed\|\|LE\|\|down\|\|4K \|\|H \|\|H
			\|\|H-
			Use 80bits extended precision see [http://en.wikipedia.org/wiki/Extended_precision extended precision]
			\|\|8
	\|\|<code>__x86_64__ && __ILP32__</code>		\|\|<code>__x86_64__ && __ILP32__</code>
	\|}		\|}